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datasheet low phase noise t1/e 1 clock generator mk1581-01 idt? / ics? low phase noise t1/e1 clock generator 1 mk1581-01 rev d 073007 description the mk1581-01 provides synchronization and timing control for t1 and e1 based network access or multitrunk telecommunication systems. the device accepts an 8 khz frame clock input and uses an on-chip vcxo to produce a synchronized low phase noise clock output. this monolithic ic, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid vcxo retiming module. through selection of external loop filter components values, the device can be tailored to meet the system?s clock jitter atten uation requirements. low-pass jitter attenuation characteristics in the hz range are possible. features ? generates a t1 (1.544 mhz) or e1 (2.048 mhz) output clock from an 8khz frame clock input ? configurable jitter attenuati on characteristics, excellent for use as a stratum source de-jitter circuit ? vcxo-based clock generation ensures very low jitter and phase noise generation ? output clock is phase and frequency locked to the input reference clock ? + 115ppm minimum crystal fr equency pullability range, using recommended crystal ? industrial temperature range ? low power cmos technology ? 16 pin tssop package ? single 3.3 v power supply block diagram charge pump vcxo pullable crystal output divider feedback divider 8khz_in clk x2 x1 iset vdd 3 vdd vin chgp 5 gnd sel phase detector c p c s r s r set
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 2 mk1581-01 rev d 073007 pin assignment 16 pin 4.40 mil body, 0.65 mm pitch tssop output clock selection table pin descriptions 12 1 11 2 10 vdd x1 3 9 vdd 4 vdd x2 5 vin 6 8khz_in 7 gnd 8 gnd sel clk gnd gnd gnd chgp iset 16 15 14 13 input clock sel output clock (mhz) crystal used (mhz) 8 khz 0 1.544 24.704 8 khz 1 2.048 24.576 pin number pin name pin type pin description 1 vdd power power supply. connect to +3.3 v. 2 vdd power power supply. connect to +3.3 v. 3 vdd power power supply. connect to +3.3 v. 4 vin input vcxo control voltage input. connect this pin to chgp pin and the external loop filter as shown in this data sheet. 5 gnd power connect to ground. 6 gnd power connect to ground. 7 gnd power connect to ground. 8 chgp output charge pump output. connect this pi n to the external loop filter and to pin vin. 9 iset ? charge pump current setting node, connection for setting resistor. 10 gnd power connect to ground. 11 gnd power connect to ground. 12 clk output clock output. 13 sel input output frequency selection. determines output frequency as per table above. internal pull-up. 14 8khz_in input 8 khz reference clock input. 15 x2 ? crystal output. connect this pin to the specified crystal. 16 x1 ? crystal input. connect this pin to the specified crystal.
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 3 mk1581-01 rev d 073007 functional description the mk1581-01 is a clock generator ic that generates a t1 or e1 reference clock directly from an internal vcxo circuit that works in conjunction with an external quartz crystal. the vcxo output frequency and phase is controlled by an internal pll (phase locked loop) circuit, enabling the device to perform clock regeneration from an 8 khz input reference clock. most typical pll clock devices use an internal vco (voltage controlled oscilla tor) for output clock generation. by using a vcxo with an external crystal, the mk1581-01 is able to generate a low jitter, low phase-noise output clock. the low bandwidth capability of the pll circuit serves to provide input clock jitter attenuation and enables stable operation with the low frequency input reference clock. the internal vcxo circuit requires an external pullable crystal for operation. external loop filter components enable a pll configuration with low loop bandwidth. application information output frequency configuration the mk1581-01 is configured to generate either a 1.544 mhz t1 clock or a 2.048 mhz e1 clock from an 8 khz input clock. please refer to the output clock selection table on page 2. input bit sel is set according to this table, as is the external crystal frequency. please refer to the quartz crystal section on this page regarding external crystal requirements. quartz crystal it is important that the correct type of quartz crystal is used with the mk1581-01. failure to do so may result in reduced frequency pullability ra nge, inability of the loop to lock, or excessive output phase jitter. the mk1581-01 operates by phase-locking the vcxo circuit to the input signal of the selected iclk input. the vcxo consists of the external crystal and the integrated vcxo oscillator circuit. to achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the pcb layout recommendations section must be followed. the frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. the mk1581-01 incorporates variable load capacitors on-chip which ?pull?, or change, the frequency of the crystal. the crystals specified for use with the mk1581-01 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pf. to achieve this, the layout should use short traces between the mk1581-01 and the crystal. a complete description of the recommended crystal parameters is in app lication note man05. a list of approved crystals is located on the idt web site (www.idt.com) . pll loop filter components a phased-locked loop (pll) is a control system that keeps the vco frequency and phase locked with the input reference clock. like all control systems, analog pll circuits use a loop filter to estab lish operating stability. the mk1581-01 uses external loop filter components for the following reasons: 1) larger loop filter capacitor values can be used, allowing a lower loop bandwidth. this enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilitie s. larger loop filt er capacitors also allow higher loop damping factors when less passband peaking is desired. 2) the loop filter values can be user selected to optimize loop response characteristics for a given application. referencing the external component schematic on this page, the external loop filter is made up of components r s , c s and c p . r set establishes pll charge pump current and therefore influences loop filter characteristics. design aid tools for configuring the loop filter can be found at www.idt.com, including on-line and pc-based calculators.
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 4 mk1581-01 rev d 073007 external component schematic recommended loop filter values vs. output frequency selection sel output freq crystal multiplier (n) r set r s c s c p loop bandwidth (-3db point) damping factor 0 1.544 mhz 3088 120 k ? 1.0 m ? 0.1 f 4.7 nf 18 hz 1.4 1 2.048 mhz 3072 120 k ? 1.0 m ? 0.1 f 4.7 nf 19 hz 1.4 c s r set r s c p refer to crystal tuning section 12 1 11 2 10 vdd x1 3 9 vdd 4 vdd x2 5 vin 6 8khz_in 7 gnd 8 gnd sel clk gnd gnd gnd chgp iset 16 15 14 13 c l c l pullable crystal
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 5 mk1581-01 rev d 073007 a ?normalized? pll loop bandwidth may be calculated as follows: the ?normalized? bandwidth (nbw) equation above does not take into account the effects of damping factor or the second pole. nbw is approximately equal to the actual -3db bandwidth of the loop when the damping factor is about 5 and c 2 is very small. in most applications, nbw is about 75% of the actual -3db bandwidth. however, nbw does provide a useful approximation of filter performance. the loop damping factor is calculated as follows: where: r s = value of resistor in loop filter (ohms) i cp = charge pump current (amps) (refer to charge pump current table, below) n = crystal multiplier shown in the above table c s = value of capacitor c s in loop filter (farads) as a general rule, the followin g relationship should be maintained between components c s and c p in the loop filter: charge pump current table special considerations must be made in choosing loop components c s and c p . these recommendations can be found in the design aid tools section of www.icst.com. series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . (the optional series termination resistor is not shown in the external component schematic.) decoupling capacitors as with any high performance mixed-signal ic, the mk1581-01 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. to further guard against interfering system supply noise, the mk1581-01 should use one common connection to the pcb power plane as shown in the diagram on the next page. the ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. n bw r s i cp 575 n ------------------------------------- ---- = d amping factor r s 625 i cp c s n -------------------------------------- ----- = c p c s 2 0 ----- - = r set charge pump current (i cp ) 1.4 m ? 10 a 680 k ? 20 a 540 k ? 25 a 120 k ? 100 a
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 6 mk1581-01 rev d 073007 recommended power s upply connection for optimal device performance crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground, shown as c l in the external component schematic. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) been the crystal and device. in most cases the load capaci tors will not be required. they should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. if the need for the load capacitors is later determined, the values will fall within the 1-4 pf range. the need for, and value of, these trim capacitors can only be determined at prototype evaluation. refer to man05 for the centering capacitor selection procedure. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. please also refer to the recommended pcb layout drawing on page 7. 1) each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no via?s should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) the loop filter components must also be placed close to the chgp and vin pins. c p should be closest to the device. coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. use of vias should be avoided. 3) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) to minimize emi the 33 ? series termination resistor, if needed, should be placed close to the clock output. 5) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the mk1581-01. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. the idt applications note man05 may also be referenced for additional suggestions on layout of the crystal section. connection to 3.3v power plane ferrite bead bulk decoupling capacitor (such as 1 f tantalum) vdd pin vdd pin vdd pin 0.01 f decoupling capacitors
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 7 mk1581-01 rev d 073007 recommended pcb layout absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the mk1581-01. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c g for minimum output clock jitter, remove ground and power plane within this entire area. also route all other traces away from this area. = ground connection g g g g g legend: for minimum output clock jitter, device vdd connections should be made to common bulk decoupling device (see text). 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 g g g g g
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 8 mk1581-01 rev d 073007 recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5%, ambient temperature -40 to +85 c ac electrical characteristics unless stated otherwise, vdd = 3.3v 5%, ambient temperature -40 to +85 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.15 +3.3 +3.45 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.3 3.45 v supply current idd clock outputs unloaded, vdd = 3.3 v 10 15 ma input high voltage, sel v ih 2v input low voltage, sel v il 0.8 v input high voltage, 8khz_in v ih vdd/2+1 v input low voltage, 8khz_in v il vdd/2-1 v input high current i ih v ih = vdd -10 +10 a input low current i il v il = 0 -10 +10 a input capacitance, except x1 c in 7pf output high voltage (cmos level) v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -8 ma 2.4 v output low voltage v ol i ol = 8 ma 0.4 v short circuit current i os 50 ma vin, vcxo control voltage v xc 0vddv nominal output impedance z out 20 ? parameter symbol conditions min. typ. max. units vcxo crystal pull range f xp using recommended crystal -115 +115 ppm vcxo crystal nominal frequency f x 24.704 24.576 mhz input jitter tolerance t ji in reference to input clock period 0.4 ui input pulse width (1) t pi 10 ns output frequency error f out iclk = 0 ppm error 0 0 0 ppm output duty cycle (% high time) t od measured at vdd/2, c l =15 pf 40 60 %
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 9 mk1581-01 rev d 073007 note 1: minimum high or low time of input clock. note 2: the input to output clock skew is not contro lled nor predictable and will ch ange between power up cycles. because it is dependent on the phase relationship between the output and feedback divider states following power up, the input to output clock skew will re main stable during a give n power up cycle. if controlled input to output skew is desired for this output clock frequency please refer to the mk2049 or mk2069 products. thermal characteristics output rise time t or 0.8 to 2.0v, c l =15 pf 1.5 ns output fall time t of 2.0 to 0.8v, c l =15 pf 1.5 ns skew, input to output clock t io note 2 cycle jitter (short term jitter) t ja peak to peak 150 ps p-p parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w parameter symbol conditions min. typ. max. units
mk1581-01 low phase noise t1/e1 clock ge nerator vcxo and synthesizer idt? / ics? low phase noise t1/e1 clock generator 10 mk1581-01 rev d 073007 package outline and package dimensions (16-pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature mk1581-01gi mk1581-01gi tubes 16-pin tssop -40 to +85 c mk1581-01gitr mk1581-01gi tape and reel 16-pin tssop -40 to +85 c mk1581-01gilf 15810gil tubes 16-pin tssop -40 to +85 c MK1581-01GILFTR 15810gil tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
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